As is well-understood in the art, lithography processes are used in the fabrication of the various layers in semiconductor wafer processing. Important to such lithography fabrication processes is the correct and accurate alignment and orientation of various fabrication layers formed on a wafer. Each of the layers formed must be aligned within a certain level of accuracy otherwise the incidence of circuitry failure in a wafer (and its associated dies) is excessive. As is also known, overlay metrology targets are used to obtain accurate measurements of target features. In particular, such targets can be used to obtain accurate measurements of overlay errors between layers. Such targets commonly include arrays of uniformly constructed and uniformly spaced periodic features arranged to provide the best possible targeting information. Typical prior art example targets include periodic gratings or periodically configured higher dimensional target arrays comprised of a plurality of uniformly spaced and sized metrology features. Additionally, so-called “box-in-box (BiB) overlay targets find common usage.
Such periodic targeting structures typically feature two layers of similarly oriented periodic gratings formed one over the other. Typically, the layers are designed with a specified predetermined offset with respect to each other. This enables scattering signals to be generated when illuminated by a light beam. A comparison of the actual signal produced with the expected scattering signal enables highly accurate overlay metrology measurements to be made.
Measurements of the targets can be used to determine whether an overlying layer formed over an underlying layer is positioned with sufficient accuracy. Correctly positioned layers indicate that the fabrication processes can progress to further processing steps without adjustment. Layers that are misaligned badly enough may impair the electrical function of the dice formed on a wafer and require a reworking of the wafer and/or adjustment of fabrication parameters to enable a more accurate placement of the overlying layer.
In the existing art, analysis of a design file (e.g., a GDS (Graphic Data System) type file or other design data file associated with relevant mask reticle information) that describes an IC layout and other relevant design data is used to determine an error overlay budget for the alignment of two overlying layers. Such an overlay error budget can be determined using overlay modeling. Typically, a single parameter is used to characterize the permissible level of overlay error in an entire layer of a wafer (or alternatively an entire stepper field).
For example, Maximum Error Prediction (MEP) may be used to obtain a model-based lot “dispositioning parameter”. This parameter describes the maximum acceptable overlay error that will result in a functional die. Commonly, this involves identifying the regions of a layer most sensitive to layer misplacement (e.g., regions likely to suffer electrical failures in the event of the smallest layer misalignment). Then the maximum amount of misplacement is determined (for example, the maximum amount of misalignment that will still result in electrically functional circuitry). In other words, a worse case modeled overlay error is determined and used as the dispositioning parameter for the entire wafer or, alternatively, the entire scanning field of the fabrication device. Thus, for the entire wafer or field, the same parameter is used. Thus, one number is used to describe the acceptable limit for error tolerance for the entire wafer (or alternatively for the entire scanning field of the fabrication device). This has the advantage of providing a quick, simple, and easily applicable parameter that currently enjoys wide applicability in the industry. However, this method has the disadvantage of imposing an unnecessarily tight tolerance on the whole wafer, when many of the areas of the wafer may not require such a tight tolerance.
Once a dispositioning parameter is determined, metrology measurements are then made of the various targets on the wafer and the degree of overlay error is determined for the wafer based on these metrology measurements. Then the determined overlay error can be compared to the dispositioning parameter. Based on this comparison, a decision regarding wafer disposition is made. Metrology measurements having overlay errors greater than the dispositioning parameter generally indicate that the wafer must be reworked or discarded as necessary. Other methods of obtaining dispositioning parameters are also known and employed to generate single value dispositioning parameters. But in all such cases, the practiced methodologies require the determination of a single worst case dispositioning parameter that is used to provide a quick and simple method of dispositioning wafers (or portions of a wafer) based on a comparison to one threshold value (dispositioning parameter).
As indicated briefly above, a disadvantage of such methods is that they operate under the assumption that the overlay error budget is equal at all points on the wafer (or across the scanner field). However, in reality, some areas of a wafer or scanner field are much more sensitive to overlay errors than others. For example, some portions of a wafer design may be more susceptible to electrical failure if the pattern is misaligned than other portions of the wafer. However, present dispositioning technologies have no way of taking this into consideration. Because existing technologies rely on a single dispositioning parameter, such a simplified analysis of a surface may result in the rejection of wafers that may, in actuality, have satisfactory electrical function. Unfortunately, this can result in the rejection of functional and satisfactory wafers requiring unnecessary reworking and/or reprocessing when they would not otherwise need such additional processing. This is time consuming, costly, and in general wasteful.
Therefore, although existing dispositioning processes and tools are generally suitable for their intended purposes, improvements can be made. The present invention seeks to go beyond the limitations and structural shortcomings of existing technologies to provide an improved method of dispositioning wafers.